1. Technical Field
This invention relates generally to data flow through a computing system. More specifically, the invention relates to a means of making a digital signal processing function perform independently of the system processor.
2. Related Art
Real-time computational systems dedicate a percentage of processing time to managing data flow through the system and between various subprocessors. The processing time which is dedicated to this function becomes substantial when the computational system has high speed real-time data arriving continuously and asynchronously. Data flow synchronization and throughput speed can also be impeded if the system processor has to handle the data directly.
When these computational systems have processing power which is decentralized and distributed over the processing path, performance is limited by the slowest part of the data path. The high performance of some components or subsystems may be lost due to the low performance of others. In these cases, throughput suffers when the computational results are interdependent, rather than independent among the subprocessors.
These performance problems are compounded when a subsystem function is performed in hardware. These hardware-based functions process data considerably faster that the system processor, resulting in a greater demand being placed on the system processor to manage the data throughput to satisfy the subprocessor's needs.
Computing systems which have high speed real-time data arriving continuously and asynchronously have implemented various techniques to synchronize to the incoming data. For example, interrupts or similar schema are commonly used to respond only when data is available. Utilization of interrupts requires additional hardware to save the full state of the processor, including the indication of the offending event, and the instructions which have to be executed after the interrupt is serviced. This tends to be inefficient, using a significant portion of the processing time to manage the data flow.
Another common solution to handling the asynchronous data flow has been to use First In First Out (FIFO) buffers to synchronize the data input or output to a processor. The FIFO will function as a temporary storage area, holding the incoming data until the processor is ready to receive it, and holding the processed output data until the receiving device is ready to receive it. With the FIFO buffers alone, the performance and speed of the signal processor will continue to have system dependencies due to the system processor having to control the data transfers between other subsystems and the digital signal processor. What is needed is a system architecture which allows sub-processing functions to be performed without the burden of being dependent upon the system environment and relieves the system processor from having to perform the function of controlling the data flow to/from the sub-processor.